As technological advances in the semiconductor industry plunge deeper into submicron geometries, the number of circuit elements increases, necessitating an increase in the number of electrical interconnects to provide the desired circuit functionality. Copper and copper alloys have become the interconnect materials of choice because of their low resistance, thereby enabling enhanced performance.
Conventional fabrication techniques comprise forming an inlaid copper wiring pattern 100 in a dielectric layer 120, as illustrated in FIG. 1A. An etch stop layer 110 is formed on an upper surface of inlaid copper 100, an interlayer dielectric 120 formed thereon, and a capping layer 130 formed on interlayer dielectric 120. A metal hardmask 140 is then formed over capping layer 130. Subsequent processing by any of various conventional techniques results in the formation of an opening, such as a dual damascene opening, in interlayer dielectric 120 through metal hardmask 140. As a result of such etching, polymeric deposits 150 typically form in the via opening portion of the dual damascene opening. Subsequently, as illustrated in FIG. 1B, the hardmask 140 is removed by wet chemical etching, as with tetramethyl ammonium hydroxide (TMAH) or tetraethyl ammonium hydroxide (TEAH). During such etching it is necessary to maintain etch stop layer 110 on the upper surface of the inlaid copper 100 to prevent oxidation and removal of copper, as such oxidation would prevent electrical contact of conductive material subsequently deposited in the opening.
Dry etching is then conducted to remove the exposed portion of etch stop layer 110 in order to expose a portion of the upper surface of the inlaid copper, as shown in FIG. 1C, resulting in additional etching residues 160, such as copper containing CF polymers. Subsequently, it is necessary to perform an additional cleaning step to remove the polymeric deposits 150 and etching residues 160, and any copper oxide that may have formed, as with dilute hydrofluoric acid (HF). An upper surface 170 of the inlaid copper is thereby cleared, as illustrated in FIG. 1D.
Such conventional practices involve a dry etching step (FIG. 1A), a wet etching step (FIG. 1B), a dry etching step again (FIG. 1C), and another wet etching step (FIG. 1D). This sequence of etching steps burdens transport capacity and increases the number of tools required and, hence, decreases manufacturing throughput.
A need therefore exists for methodology enabling the fabrication of semiconductor devices having features in the deep submicron range utilizing a metal hardmask and forming copper and copper alloy interconnects, with improved efficiency and increased manufacturing throughput.